Cellular mosfet devices and their manufacture

ABSTRACT

A cellular MOSFET device has a cellular area (CA) comprising active MOSFET cells, and one or more Schottky diode areas (SA) accommodated within a deep end region ( 15 ) at a lateral boundary of this cellular area (CA). This deep end region ( 150 ) is laterally divided so as to accommodate the diode area (SA) therein. A diode portion ( 14   d ) of the first conductivity type of the drain region ( 14 ) extends upwardly through the laterally-divided deep end region ( 150 ) that is of the second conductivity type. The Schotty barrier ( 100 ) formed with this diode portion ( 14   d ) terminates laterally in the laterally-divided portions ( 150   deep end region (   150 ) which serve as a guard region and field-relief region for the Schottky diode.

This invention relates to cellular MOSFET devices (i.e. cellularinsulated-gate field-effect transistor devices), and to theirmanufacture. The invention relates particularly to the integration of aSchottky diode at a diode area of the body, in parallel with aconduction channel of the MOSFET.

Cellular insulated-gate field-effect transistor devices are well knownas power switches in a variety of applications. The devices compriseactive device cells in a cellular area of a semiconductor body. Eachactive device cell has a channel-accommodating region of a secondconductivity type between a surface-adjacent source region and anunderlying drain region that are of a first conductivity type. A gateelectrode is dielectrically coupled to the channel-accommodating regionfor controlling a conduction channel between the source and drainregions in operation of the device. Although commonly designated“MOSFET”, it should be noted that the gate electrode need not be metal(but is often of conductively-doped polysilicon) and that the gatedielectric need not be oxide. The MOSFET cells may be of DMOS type(having a planar gate at the body surface) or of trench-gate type(having the gate in a trench extending through the channel-accommodatingregion). Typically, the cellular area is laterally bounded by an endstructure including a deep end region of the second conductivity typethat adjoins the channel-accommodating region. This end region has agreater depth and a higher doping concentration than thechannel-accommodating region.

It is known from United States patent U.S. Pat. No. 4,521,795 (Philipsref: PHB32842) to incorporate a Schottky diode at a diode area of thedevice body, in parallel with the MOSFET channel. By this means, theswitching speed of the MOSFET (e.g. when switching inductive loads) canbe increased, as the Schottky diode limits charge storage at the p-njunctions between the drain region and the channel-accommodating regionsin the device cells. The Schottky diode comprises a Schottky barrierintegrated between the source electrode (connected to the source regionand channel-accommodating region) and a diode portion of the drainregion that is of the first conductivity type. In the specificembodiments depicted in U.S. Pat. No. 4,521,795, Schottky diode areasare incorporated in the MOSFET cells, with the Schottky barrierspreferably terminating laterally in an edge of the channel-accommodatingregion that serves as a guard ring for the Schottky diode.

U.S. Pat. No. 4,521,795 discloses Schottky diode integration with bothDMOS-type cells and trench-gate cells. United States patent U.S. Pat.No. 6,049,108 and published PCT international patent applicationWO-00/51167 disclose various specific layout geometries for integratingSchottky diodes in trench-gate MOSFET designs. In particular, U.S. Pat.No. 6,049,108 teaches dedicating a selected number of the cells to suchdiodes at predetermined locations in the cellular area, whereasWO-00/51167 discloses integrating the diodes between neighbouringtrench-gates in, for example, an elongate stripe cell geometry. Thewhole contents of U.S. Pat. No. 4,521,795, U.S. Pat. No. 6,049,108 andWO-00/51167 are hereby incorporated herein as reference material.

It is an aim of the present invention to integrate such a Schottky diodein a more advantageous configuration within the MOSFET device, with goodSchottky characteristics, and to permit such integration in a simple,reliable and low-cost manufacturing process.

According to a first aspect of the invention, in a cellular MOSFETdevice having a cellular area comprising active MOSFET cells, theSchottky diode area is accommodated within the deep end region at alateral boundary of this cellular area. This deep end region islaterally divided so as to accommodate the diode area therein. A diodeportion of the first conductivity type of the drain region extendsupwardly through the laterally-divided deep end region that is of thesecond conductivity type. The Schottky barrier formed with this diodeportion terminates laterally in the laterally-divided portions of thedeep end region which serve as a field-relief region for the Schottkydiode.

Such an integration scheme in accordance with the invention has severaladvantages.

The overall size and pitch of the active device cells is not affected bythis Schottky diode integration, and so the active device cells can becompact. As such, a compact cellular layout with high current capabilityand low on-resistance can be maintained for the MOSFET.

However, there is plenty of layout area available for accommodating theSchottky diode in end structures at the lateral boundary of a cellulararea. As such, one or more Schottky barriers of large area can beaccommodated in a compact manner in the device. Thus, the Schottky diodeareas may be accommodated in one or more stripes that extend betweencellular areas of the device and/or that extend around a perimeter ofthe whole cellular area of the device. The deep end regions can bedistributed around and throughout the whole active area of the MOSFET,so suppressing parasitic bipolar transistor effects between the sourceand drain regions and improving the MOSFET ruggedness. These deep endregions are particularly beneficial for incorporation at the boundary ofcellular areas that comprise trench-gate cells, when the deep endregions are deeper than the gate trenches.

Because of their depth, the laterally-divided end-region portionsprovide good relief of the electric field in the diode portion of thedrain region that they laterally bound. The Schottky diode can thereforehave good blocking characteristics. Indeed, the laterally dividedportions of the deep end region may even have a sufficiently closespacing as to permit depletion of the diode portion of the drain region(across this close spacing) in a blocking state of the device. This isadvantageous for the field-relief and for achieving a compact structure.

Field trenches containing insulating material may be included in thefield-relief region of the diode in order to reduce field spreadingbeneath the deep end region at the lateral boundary of the diode portionof the drain region. Thus, the device may comprise one or more suchfield trenches which extend to a greater depth in the body than the deepend region and which laterally bound the portions of the deep end regionthat provide the guard region and field-relief region. However,particularly where a Schottky diode area is accommodated betweencellular areas, the laterally-divided deep end region may provide asimple field-region structure for the diode without any field insulatorin this area.

According to a second aspect of the present invention, there is provideda method of manufacturing such cellular MOSFET devices with integratedSchottky diodes, wherein the method comprises the steps of:

(a) providing the device body having a semiconductor body portion of afirst conductivity type for a drain region of the MOSFET device,

(b) locally doping the body to provide an end region of the secondconductivity type for an end structure at a lateral boundary of an areaof the body that provides the cellular area, which end region islaterally divided to accommodate the diode area within the end region ofthe end structure, with a diode portion of the drain region extendingupwardly through the end region,

(c) forming the active device cells in the cellular area, wherein thecells have a channel-accommodating region of a second conductivity typethat adjoins the end region at a boundary of the cellular area, andwherein the end region resulting from the local doping of step (b) has agreater depth and a higher doping concentration than thechannel-accommodating region, and

(d) forming at the diode area the Schottky barrier which terminateslaterally in the laterally divided portions of the end region, whichlaterally divided portions serve as a guard region and field-reliefregion for the Schottky diode.

This aspect of the invention permits integration of the Schottky diodein the MOSFET device by means of a simple, reliable and low-costmanufacturing process and with good Schottky characteristics.

Various masking material layers may be provided over the diode area tomask the diode area during the formation of the active device cells instep (c).

Typically, the device termination structure may comprise a fieldinsulator. In this case, an extra area of the field insulator may beprovided also over the diode area before step (c) and serve to mask thediode area during the formation of the active device cells. This extrafield-insulator area can then be removed from the diode area beforeforming the Schottky barrier in step (d).

In the case of a trench-gate MOSFET device, the gate trench is etchedinto the body in step (c) at windows in an etch-mask layer. In thiscase, an area of the etch-mask layer may be provided over the diode areato mask the diode area during the formation of the active device cellsin step (c). This area of the etch-mask layer is removed from the diodearea before forming the Schottky barrier in step (d).

Various advantageous features and feature-combinations in accordancewith the present invention are set out in the appended claims. These andothers are illustrated in embodiments of the invention that are nowdescribed, by way of example, with reference to the accompanyingdiagrammatic drawings, in which:

FIG. 1 is a simple plan view of one example of a trench-gate cellularMOSFET device in accordance with the invention, showing bothedge-termination and cross-area configurations for deep end regions thatlaterally bound cellular areas;

FIG. 2 is a cross-sectional view of one example of a cross-area deep endregion of such a device as FIG. 1, taken on the line II—II of FIG. 1,i.e. between two cellular areas;

FIG. 3 is a cross-sectional view of one example of an edge-terminationdeep end region of such a device as FIG. 1, taken on the line III—III ofFIG. 1;

FIGS. 4 to 6 are cross-sectional views of the device part of FIG. 2 atsuccessive stages in its manufacture by one example of a method inaccordance with the present invention;

FIG. 7 is a cross-sectional view of another example of anedge-termination structure also in accordance with the invention(similar to that of FIG. 3 but including also deep field trenches), onwhich are superimposed simulation plots of electric field lines anddepletion layers in a blocking state of the Schottky diode;

FIG. 8 is a simulation plot of leakage current Ir in 10⁻³ Amps againstreverse voltage Vr in volts, for a Schottky diode having a deepend-region and field-trench boundary as in FIG. 7, as compared with aSchottky diode having a trench-gate boundary;

FIG. 9 is a cross-sectional view of the device part of an edgetermination structure, similar to that of FIG. 7, at a stage in itsmanufacture also in accordance with the present invention; and FIG. 10is a cross-sectional view, similar to FIG. 3, of the device part of anedge termination structure of a modification also in accordance with theinvention, having side-by-side Schottky diodes in the end region.

Apart from the simulation plots of FIGS. 7 and 8, all the drawings arediagrammatic, with the relative dimensions and proportions of variousparts of their Figures being shown exaggerated or reduced in size, forthe sake of clarity and convenience in the drawings. Thus, for example,the different spacings between the gate trenches in FIGS. 1 and 2illustrate the degree to which the proportions are exaggerated orreduced in respective drawings, for convenience and clarity. The samereference signs are generally used to refer to corresponding or similarfeatures in modified and different embodiments.

FIGS. 1 to 3 illustrate an exemplary embodiment of a cellular powerMOSFET in accordance with the present invention. In the cellular areasCA of this device, each transistor cell has a channel-accommodatingregion 15 of a second conductivity type (p-type in this example) thatseparates source and drain regions 13 and 14, respectively, of a firstconductivity type (n-type in this example). The drain region 14 iscommon to all the cells.

Being a MOSFET of the trench-gate type, the device has its gateelectrode 11 in an insulated trench 20 that extends through the regions13 and 15 into an underlying portion of the drain region 14. Theindividual cells (of elongate stripe geometry in FIG. 1) are laterallybounded by this trench-gate 11. In the simplified depiction of FIG. 1,the continuous trench-gate 11 is represented by a broken line (fordistinction in the drawing from deep end regions that are describedbelow). The gate 11 is capacitively coupled to the region 15 by anintermediate dielectric layer (not shown), i.e. at the insulated wallsof the trench 20. The application of a voltage signal to gate 11 in theon-state of the device serves, in known manner, for inducing aconduction channel in the region 15 and for controlling current flow inthis channel between the source and drain regions 13 and 14.

The source region 13 is located adjacent to the top major surface 10 aof the device body 10, where regions 13 and 15 are contacted by a sourceelectrode 23. The trench-gate 11 is insulated from the overlyingelectrode 23 by an intermediate insulating overlayer 18 (sometimestermed “capping” layer 18). The region 14 is a drain-drift region, whichmay be formed by an epitaxial layer of high resistivity on a morehighly-doped substrate 14 a of the same conductivity type. The substrate14 a is contacted at the bottom major surface 10 b of the device body 10by a drain electrode 24. Thus, the MOSFET of FIGS. 1 to 3 is a verticalpower device structure.

The specific cellular device shown in FIG. 1 comprises four cellularareas CA, each of which has a respective end structure at its lateralboundary. The end structure is either an annular edge termination (FIG.3) in the annular peripheral area PA of the device or a cross stripestructure (FIG. 2) that extends between neighbouring cellular areas CA.In each case, the end structure includes an end region 150 of the secondconductivity type (i.e. p-type in this example) that extends to agreater depth in the body 10 than do the channel-accommodating region 15and the gate trench 20.

The end region 150 adjoins the channel-accommodating region 15 and has ahigher doping concentration P+ than the channel-accommodating region 15.In the simplified depiction of FIG. 1, the lateral perimeters of theseend regions 150 are represented by continuous lines. In the specificembodiment as depicted in FIG. 1, the end regions 150 of both theannular edge termination and the two cross stripes merge together toform a continuous network pattern. However, the cross stripes 150 c and150 b may terminate short of the annular termination region 150 e and soform one or more separate islands in the layout pattern of the endregion 150. Although FIG. 1 shows only four cross stripes 150 c and 150b, a larger number of cross stripes or islands 150 c and 150 g may beincluded in the layout pattern of the end region 150. Indeed, a largedistribution of the deep end regions 150 among the cellular areas CA isbeneficial in suppressing parasitic bipolar transistor effects betweenthe source and drain regions 13 and 14 and improving the MOSFETruggedness.

In accordance with the present invention, one or more of the deep endregions 150 of these respective end structures in the device of FIGS. 1to 3 are laterally divided to accommodate a Schottky diode area SAwithin the deep end region 150. By way of example, FIG. 1 illustratesthe incorporation of four such diode areas SA within the annulartermination region 150 e and two such diode areas SA within the crossstripe regions 150 c. For clarity in the drawing, these diode areas SAare hatched in the plan view of FIG. 1.

At each diode area SA of the body 10, the MOSFET device comprises aSchottky diode connected in parallel with the conduction channel of theMOSFET. Thus, the diode has a Schottky barrier 100 integrated betweenthe source electrode 23 and a diode portion 14 d of the drain region 14.This diode portion 14 d of the first conductivity type (i.e. n-type inthis example) extends upwardly through the laterally-divided deep endregion 150 of the second conductivity type (i.e. p-type in thisexample), to the body surface 10 a. The Schottky barrier 100 terminateslaterally in the laterally divided portions 150 f of the deep end region150, which serve as a guard region and field-relief region for theSchottky diode.

Because of their depth, these laterally-divided portions 150 f providegood relief of the electric field in the drain portion 14 d that theylaterally bound. Thus, the depletion layer formed in a blocking state ofthe device spreads laterally from the p-n junctions with the portions150 f, as well as vertically from the Schottky barrier. The Schottkydiode can therefore have good blocking characteristics. FIGS. 2 and 3diagrammatically show quite a large spacing SY for these field-reliefportions 150 f. However, it should be understood that the spacing SY ofthe portions 150 f can be quite small, for example sufficiently close asto permit depletion of the diode portion 14 d of the drain region 14(across this close spacing) in the blocking state. This is advantageousfor both increased field-relief and for achieving a compact structure.

In the particular embodiment illustrated in FIG. 1, the layout of eachof the Schottky diode areas SA is of an elongate stripe geometry. Thiselongate geometry permits the achievement of both a close spacing SY ofthe field-relief portions 150 f (i.e. across the stripe) and a largearea for the Schottky barrier 100 (i.e. due to the length of thestripe). However, other layout shapes may be adopted for a Schottkydiode area SA, where such would fit within the layout geometry of thedeep end region 150.

FIG. 1 shows six separate areas SA in the end-region network 150 e and150 c. However, these separate areas may merge together into acontinuous area SA so as to maximize the area of the Schottky diode.This can save layout area in integrating the Schottky diode, and thespacing SY can be keep small for a given Schottky barrier area andforward voltage of the diode (that is proportional to the Schottkybarrier area).

FIG. 3 illustrates a Schottky diode area SA in the annular edgetermination region 150 e around the annular peripheral area PA of thedevice. In the particular embodiment illustrated in FIG. 1, these diodeareas SA extend around most of the device perimeter. As is usual for aMOSFET, the device termination structure also includes a field insulator155, typically comprising one or more layers of silicon dioxide and/orsilicon nitride. This field insulator 155 adjoins the deep end region150 e where the diode area SA is accommodated but is absent from thedrain portion 14 d of the diode. FIG. 3 also illustrates inclusion, onthe field insulator 155, of an outwardly-directed field plate 110 g thatis connected to the MOSFET gate 11 and an inwardly-directed field plate110 d that is connected to the MOSFET drain region 14. The gateconnection for field plate 110 g is provided at lateral extensions 11 eand 20 e of the gate 11 and trench 20 in the deep termination region 150e, as illustrated in FIG. 3.

FIG. 2 illustrates the inclusion of a Schottky diode area SA in a crossstripe region 150 c that extends between two neighbouring cellular areasCA. As shown in FIG. 1, the active device cells of these two areas CAhave their stripe-shaped cell geometry parallel to the region 150 c. Inthe simple and compact form illustrated in FIG. 2, there is an absenceof the field insulator 155 from the region 150 c.

In the specific embodiment of FIG. 1, no diode area SA is included inthe cross stripe region 1 sob. Instead, the stripe region 150 b formspart of a gate bus-bar structure that carries a metal gate-connectiontrack (not shown) between neighbouring cellular areas CA. The region 150b extends to a further part 150 g of the deep end region 150 that islocated below the metal gate-terminal bond-pad (also not shown). Themetal gate-connection track and the metal gate-terminal bond-pad areconnected to lateral extensions 11 b of the trench-gate 11 in the parts150 b and 150 g of the deep end region 150.

Typically, the semiconductor device body 10 is of monocrystallinesilicon. In a specific example for a 30v device, the various regions ofthe device may be as follows.

The drain drift region 14 (typically an epitaxial layer) may have auniform doping n of about 2×10¹⁶ or 3×10¹⁶ phosphorus or arsenic cm⁻³,or it may have a graded doping from about 1×10¹⁶ cm³ at the surface 10 ato about 3×10¹⁷ cm⁻³ adjacent to the substrate 14 a. This doping and thethickness of the region 14 depends on the desired voltage blockingcapability of the device. In order to form the Schottky barrier 100 ofdesired barrier height to the drain portion 14 d with this doping, it isadvantageous to include a silicide layer 23 d at the body surface 10 a.Thus, the bulk of the source electrode 23 may be of an aluminium-siliconalloy and the layer 23 d may be of, for example, titanium silicide. Thissilicide layer 23 d forms an ohmic contact to the field-relief portions150 f in the diode area SA. The silicide layer 23 d may also be includedin the active cell areas CA to form good ohmic contacts between thesource electrode 23 and the channel region 15 and source region 13 andso reduce source contact resistance.

In a specific example, the doping of P+ region 150 may be about 10¹⁸boron cm⁻³, whereas that of the channel-accommodating region 15 istypically about 10¹⁷ boron cm⁻³. The depth (from the surface 10 a) of P+region 150 may be about 2.5 μm (micrometres), for example approachingtwice that of the region 15 for a trench-gate depth of about 1.5 μm or1.7 μm. In the blocking state of the MOSFET, the greater doping anddepth of the P+ region 150 pushes the depletion layer (in region 14)further towards the substrate 14 a in this boundary area of the cellularareas CA and diode areas SA. This is advantageous in increasing thefield-relief for the Schottky diode accommodated in this deep region150, as well as in improving the MOSFET ruggedness against breakdown inthe active cells of the adjacent areas CA.

The gate dielectric layer is typically of thermally grown silicondioxide or of deposited silicon dioxide, although it may comprisesilicon nitride. Typically, the trench-gate 11 is of conductively-dopedpolysilicon, although it may comprise a silicide and/or a refractorymetal.

The Schottky diode areas SA can be integrated in the device of FIGS. 1to 3 in a simple, reliable and low-cost manner, using the followingprocess technology that is also in accordance with the presentinvention. In broad overview, the process includes the steps of:

(a) providing a semiconductor wafer body 100 having a body portion 14′of the first conductivity type for the drain drift region 14 of theMOSFET device,

(b) locally doping the body to provide the end region 150 of the secondconductivity type, including the laterally divided portions 150 f in itslayout to accommodate the diode areas SA within the end region 150,

(c) forming the active device cells in the cellular area CA, and

(d) forming, at the diode areas SA, the Schottky barrier 100 whichterminates laterally in the laterally divided portions 150 f of the endregion 150.

Typically an n-type epitaxial layer having a doping as specified aboveis provided to form the body portion 14′ for the drain drift region 14.FIG. 4 illustrates stage (b) with a boron ion implantation 50 to providethe P+ region 150 in the epitaxial layer 14′. The layout pattern of theP+ region 150 as illustrated in FIG. 1 is defined by an implantationmask 55, for example of photoresist. In a specific example, a boron doseof about 5×10¹³ cm⁻² ions may be implanted at an energy of about 250keV. The dose and energy are chosen to make the region 150 more highlydoped (P+) than the later-provided channel-accommodating region 15 anddeeper in the body 10 than the region 15 and the later-etched trench 20,20 e.

After removing the mask 55, the field insulator 155 is then provided inthe peripheral area PA for the device termination and additionally overthe diode areas SA. Thus, additional areas of field insulator 155 areprovided over the diode areas SA in the device termination and in the P+cross regions 150 c.

FIG. 5 shows the additional area 155 c of the field insulator layer fora P+ cross region 150 c. The field insulator 155, typically a thickoxide layer, is preferably of deposited material, rather than athermally grown (LOCOS) oxide. Deposition of the material has lesseffect on the boron doping concentration of the underlying P+ region150.

The field insulator layer 155 serves to mask the peripheral area PA anddiode areas SA of the epitaxial layer 14′ during the formation of theactive device cells, as illustrated by additional area 155 c in FIG. 6.The active device cells can be formed in known manner, for example, with(in broad overview) the following stages:

(c)(i) etching the gate trench 20 (and its extension 20 e) at windows ina trench-etch mask;

(c)(ii) lining the trench 20 (and its extension 20 e) with the gatedielectric, for example by oxidation of the sidewalls and bottom of thetrench;

(c)(iii) providing the gate 11 (and its extensions 11 e and, forexample, any extensions thereof as part of a field-plate) by depositionand etch-patterning;

(c)(iv) implanting the channel-accommodating region 15 and source region13, and

(c)(v) forming the insulating capping layer 18 on the trench-gate 11 bydeposition or oxidation, and usually also increasing the doping of theregion 13 adjacent to the surface 10 a.

During these stages (c)(i) to (c)(v), the additional areas of the fieldinsulator layer 155 masks the diode areas SA. These additional areas aresubsequently removed from the diode areas SA before forming the silicidelayer 23 d to provide the Schottky barrier 100 in step (d). Thus, theadditional area 155 c is removed, as shown in the corresponding devicepart of FIG. 2.

The silicide layer 23 d may be deposited on the silicon surface 10 a,and/or the silicide-forming metal (for example, titanium) may be alloyedinto the silicon surface 10 a.

Thereafter, the manufacture is completed in known manner. Thus, one ormore metal layers (for example, comprising aluminium) are deposited anddefined in a photolithographic and etching step into the desired patternfor the source electrode 23 and the metal gate-connection track and thegate bond-pad. For this purpose, multiple-levels of metal (withintermediate dielectric) may be used, particularly if metal parts aredesired for field-plates (such as 110 g and 110 d of FIG. 3). The backsurface 10 b is then metallised to form the drain electrode 34, afterwhich the wafer body 100 is divided into the individual device bodies10.

It will be evident that many modifications and variations are possiblewithin the scope of the present invention. Considerable flexibility ispossible in the specific technologies and constructions that can be usedin providing and defining the regions and layers 14, 155, 150, 11, 15,13, 18, 23 d, 23 etc.

FIG. 7 illustrates one important modification in the field-reliefstructure for the Schottky diode. In this device, the MOSFET terminationstructure includes a field insulator 155 x accommodated in a fieldtrench 255 that extends to a greater depth in the body than both thedeep end region 150 and the gate trenches 20, 20 e. Preferably the fieldtrench 255 x extends close to the interface with the substrate 14 a oreven into the substrate 14 a. For a given breakdown voltage, the spacingSY in the FIG. 7 diode can be larger than that for the diode of FIGS. 2and 3.

In this embodiment of the invention, the trenched field insulator 155 xlaterally bounds the laterally-divided portions 150 f of the deep endregion 150 e that provide the guard region and field-relief region forthe Schottky diode. The inclusion of these field trenches 255 serves toreduce field spreading beneath the deep end region 150 e at the lateralboundary of the diode portion 14 d of the drain region 14, asillustrated by the plots in FIG. 7. Thus, in FIG. 7, the extent of thedepletion layer in the regions 14 and 150 e is represented by the brokenline 40, whereas the solid lines represent the electric field in theseregions 14 and 150 e and in the dielectrics 155 x and 155.

It can be seen from FIG. 7, that the potential lines in the drainportion 14 d of the diode are well spread (with no field peakconcentrations), and are well balanced between the P+ field-reliefportions 150 f at opposite sides of the spacing SY. Thus, the potentialcontours are relatively flat as they cross the Schottky spacing SY. Thisis due to the effect of the dielectric 155 x in the bounding trenches255 in spreading the potential contours, thereby raising the reversebreakdown of the Schottky diode. Thus, the breakdown of the Schottkydiode is considerably higher than the breakdown of the activetrench-gate MOSFET area. Breakdown will occur in the MOSFET active area,without the usual high leakage current normally seen with planarSchottky diodes, because the Schottky diode is still far from reachingit reverse breakdown limit.

FIG. 8 shows a simulation of the near ideal breakdown characteristic(plot B) that results from adopting a FIG. 7 field-relief structure forthe Schottky diode. Two plots of leakage current Ir in 10⁻³ Amps againstreverse voltage Vr in volts at 100° C. are given in FIG. 8. Plot B isfor a Schottky diode having a deep end region and deep field trenchconfiguration as in FIG. 7. Plot C is for a Schottky diode having ann-type diode portion 14 d of width SY, that is laterally bounded bytrench-gates of the MOSFET cells, i.e. similar to the Schottky diodestructures disclosed in U.S. Pat. No. 6,049,108 and WO-00/51167. In eachcase, the area of the Schottky barrier 100 was 2 mm², with a width SY of1 μm. As can be seen from plot C, the leakage current from thecomparison diode is already almost 1 milliAmp at a reverse voltage of30V. The diode of FIG. 7 configuration has still a minimum leakagecurrent at 30V, with no significant increase until an abrupt breakdownat 60V. Indeed, as depicted by plot B, the FIG. 7 diode substantiallyexhibits a typical MOSFET-like leakage profile, but with an increasedreverse breakdown capability. A comparable plot is obtainable for theFIG. 3 diode, i.e. with a minimum leakage current still at 30V, but witha lower increased reverse breakdown capability, for example in the rangeof 45V to 50V.

Typically, for both FIGS. 3 & 7 diodes, the spacing SY can be upwardfrom about 1 μm or less. However, it is more difficult to achieve a veryhigh breakdown for the FIG. 3 Schottky diode (without field-oxidetrenches 155 x,255). If the spacing SY in this diode is made too large,then depletion-induced lowering of its barrier height can occur.Effectively, this means an increase in its leakage current. Hence, thespacing SY in the FIG. 3 diode should be kept small in order to achievea low leakage current with effective field relief from the regions 150f.

The FIG. 7 diode structure can be formed readily by etching the fieldtrenches 255 after the P+ doping stage of FIG. 4 and before depositingthe field insulator 155, 155 x. FIG. 9 illustrates a particularlyadvantageous embodiment of how it may be incorporated into the devicetermination. In this embodiment, the diode area SA is masked with atrench-gate etch-mask layer 65 during the formation of the active devicecells in step (c). Thus, as in FIGS. 1 to 6, the MOSFET device is of thetrench-gate type, having its gate electrode 11 accommodated in a trench20. The trench 20 is etched into the body in step (c)(i), at windows inan etch-mask layer 65 that is shown in FIG. 9. This etch-mask layer 65may be of, for example, silicon nitride on a thin oxide layer on thebody surface 10 a.

In this particular method of manufacture in accordance with theinvention, an additional part 65 x of the etch-mask layer 65 is providedover the diode area SA to mask the diode area SA during the cellformation in steps (c)(i) to (c)(v). FIG. 9 illustrates the situationduring the etching of the gate trenches 20 in step (c)(i). The part ofthe layer 65 on the cellular areas CA in FIG. 9 is the first to beremoved as appropriate for carrying out the steps (c)(ii) to (c)(v).Only thereafter, the part 65 x is removed from the diode area SA for theformation of the Schottky barrier 100 in step (d). Part of the etch-masklayer 65 may be retained in the device termination as a part of thefield insulator.

Many other modifications and variations will be apparent to the personskilled in the art.

FIGS. 1 to 7 show only one diode area SA in each laterally-divided deepend region 150. However, a plurality of such diode areas SA (forexample, side-by-side stripes) may be provided in one laterally-divideddeep end region 150. FIG. 10 illustrates one such modification of theFIG. 3 diode, having two side-by-side stripe areas each of width SY.More than two such side-by-side areas may be included, for example toreduce the individual widths SY or to increase the total area of theSchottky barrier 100.

As already described, it is desirable to have a small spacing SY for theSchottky diodes of FIGS. 2 & 3 in order to achieve a low leakage currentwith effective field relief from the regions 150 f without field-oxidetrenches 155 x, 255. Otherwise, depletion induced lowering of theSchottky barrier height can occur. This assumes a typical situation inwhich the doping concentration (P+) of the regions 150 f is so high thatthe spread therein of the depletion layer is small.

However, an alternative approach is possible using a lower dopingconcentration. In this case, the laterally divided end regions 150, 150f may be implanted with such a doping concentration and profile thatcharge balance is achieved between the p-type depleted portions 150 fand the n-type depleted portion 14 d. Such charge balance is a modifiedapplication of the teaching of U.S. Pat. No. 4,754,310 (Philips ref:PHB32740), the whole contents of which are hereby incorporated herein asreference material. By this modification, the breakdown capability ofthe integrated Schottky diodes of FIGS. 2, & 10 can be much improved andthe leakage current can be reduced. This would permit the spacing SY tobe increased.

Instead of forming the drain-drift region 14 by an epitaxial layer on ahigher-doped substrate 14 a, the higher doped region 14 a of somediscrete devices may be formed by dopant diffusion into the back surface10 b of a high-resistivity substrate that provides the drift region 14.

Vertical discrete devices have been described so far, having theirsecond main electrode 24 contacting the substrate or other highly-dopedregion 14 a at the back surface 10 b of the body 10. However, anintegrated device is also possible in accordance with the invention. Inthis case, the region 14 a may be a doped buried layer between a devicesubstrate and the epitaxial low-doped drain region 14. This buried layerregion 14 a may be contacted by an electrode 24 at the front majorsurface 10 a, via a doped contact region which extends from the surface10 a to the depth of the buried layer.

The particular examples described above are n-channel devices, regions13 and 14 are of n-type conductivity, regions 15, 150 and 35 are p-type,and an electron inversion channel is induced in region 15 by the gate11. By using opposite conductivity type dopants, a p-channel device canbe manufactured by a method in accordance with the invention. In thiscase, the regions 13 and 14 are of p-type conductivity, the regions 15,150 and 35 are n-type, and a hole inversion channel is induced in theregion 15 by the gate 11.

Although the embodiments so far shown are of the trench-gate type, thepresent invention may also be used to integrate Schottky diode areas SAinto laterally-divided deep end regions 150 of MOSFETs of the DMOS type.

Semiconductor materials other than silicon may be used for devices inaccordance with the invention, for example silicon carbide.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the art and which may be used instead of or in additionto features already described herein.

Although claims have been formulated in this Application to particularcombinations of features, it should be understood that the scope of thedisclosure of the present invention also includes any novel feature orany novel combination of features disclosed herein either explicitly orimplicitly or any generalisation thereof, whether or not it relates tothe same invention as presently claimed in any claim and whether or notit mitigates any or all of the same technical problems as does thepresent invention.

The Applicants hereby give notice that new claims may be formulated toany such features and/or combinations of such features during theprosecution of the present Application or of any further Applicationderived therefrom. Thus, for example, the embodiment of FIGS. 7 and 9keeps the P+ field portions 150 f of the end region 150 in the diodearea SA. However, an integrated Schottky diode structure could be formedhaving its n-type drain diode portion 14 d laterally bounded (throughoutits depth from the surface 10 a) by the insulator-filled field trenches255,155 x, i.e. without the field portions 150 f. In the manufacture ofthis modified diode, the lateral spacing SY that divides the end region150 (in a modification of FIG. 9) may be made wider, so that the etchingof field trenches 255 removes the P+ portions 150 f. Such a diodestructure is much less advantageous than that of FIG. 7. However, such aSchottky diode structure (with the field-insulator trenches 155 x,255,but without the field portions 150 f) is apparently novel. Accordingly,the Applicants reserve the right to file patent claims to such aSchottky diode structure in the course of the prosecution of the presentpatent Application or of any further Application derived therefrom.

1. A cellular MOSFET device comprising active device cells in a cellulararea of a semiconductor body, wherein: each active device cell has achannel-accommodating region of a second conductivity type between asurface-adjacent source region and an underlying drain region that areof a first conductivity type, a gate electrode dielectrically coupled tothe channel-accommodating region for controlling a conduction channelbetween the source and drain regions in operation of the device, and asource electrode connected to the source region and to thechannel-accommodating region; the cellular area is laterally bounded byan end structure including a deep end region of the second conductivitytype that adjoins the channel-accommodating region and has a greaterdepth and a higher doping concentration than the channel-accommodatingregion; the device also comprises, at a diode area of the body, aSchottky diode having a Schottky barrier that is integrated between thesource electrode and a diode portion of the drain region that is of thefirst conductivity type; and the deep end region is laterally divided toaccommodate the diode area within the deep end region of the endstructure, with the diode portion of the first conductivity typeextending upwardly through the deep end region of the secondconductivity type, and with the Schottky barrier terminating laterallyin the laterally divided portions of the deep end region which serve asa field-relief region for the Schottky diode.
 2. A device according toclaim 1, wherein the deep end region extends around a perimeter of thedevice as part of a device termination structure and also extends acrossat least part of the device as a stripe structure between active devicecells to accommodate the diode area as a stripe between two cellularareas of the device.
 3. A device according to claim 1 or claim 2,wherein the deep end region is part of a device termination structurethat extends around a perimeter of the device, and the diode area isaccommodated around at least a part of the perimeter of the device.
 4. Adevice according to claim 2, wherein the active device cells are of astripe-shaped geometry parallel to the stripe structure thataccommodates the diode area.
 5. A device according to claim 2 or claim4, wherein the device termination structure includes a field insulatorthat is absent from the stripe structure.
 6. A device according to claim2, wherein the device termination structure includes a field insulatoradjacent to the deep end region where the diode area is accommodated inthe termination structure.
 7. A device according to claim 6, wherein thefield insulator comprises deposited insulating material accommodated ina field trench, which trench extends to a greater depth in the body thanthe deep end region and laterally bounds the portions of the deep endregion that provide the field-relief region of the diode.
 8. A deviceaccording to claim 7, wherein the gate is a trench-gate accommodated inan insulated gate trench that extends from the source region through thechannel-accommodating region and into the underlying drain region, andthe insulated gate trench is shallower than the field trench.
 9. Adevice according to claim 1, wherein the gate is a trench-gateaccommodated in an insulated gate trench that extends from the sourceregion through the channel-accommodating region and into the underlyingdrain region, and a lateral extension of the insulated gate trenchterminates in the deep end region as part of a device terminationstructure, the deep end region being deeper than the insulated gatetrench and its lateral extension.
 10. A device according to claim 1,wherein there is a sufficiently close spacing of the laterally dividedportions of the deep end region to permit depletion of the diode portionof the drain region across this close spacing in a blocking state of thedevice.
 11. A method of manufacturing a cellular MOSFET devicecomprising active device cells in a cellular area of a semiconductorbody and also comprising, at a diode area of the body, a Schottky diodehaving a Schottky barrier that is integrated between a diode portion ofthe drain region and a source electrode, wherein the method comprisesthe steps of: (a) providing the semiconductor body having a body portionof a first conductivity type for a drain region of the MOSFET device,(b) locally doping the body to provide an end region of the secondconductivity type for an end structure that laterally bounds an area ofthe body that provides the cellular area, which end region is laterallydivided to accommodate the diode area within the end region of the endstructure, with a diode portion of the drain region extending upwardlythrough the end region, (c) forming the active device cells in thecellular area, each cell having a channel-accommodating region of asecond conductivity type between a surface-adjacent source region andthe underlying drain region that are of a first conductivity type, and agate electrode that is dielectrically coupled to thechannel-accommodating region for controlling a conduction channelbetween the source and drain regions in operation of the device, whereinthe end region resulting from the local doping of step (b) adjoins thechannel-accommodating region and has a greater depth and a higher dopingconcentration than the channel-accommodating region, and (d) forming atthe diode area the Schottky barrier which terminates laterally in thelaterally divided portions of the end region, which laterally dividedportions serve as a field-relief region for the Schottky diode.
 12. Amethod according to claim 11, wherein the device termination structureincludes a field insulator, an extra area of which is provided over thediode area before step (c), serves to mask the diode area during theformation of the active device cells, and is removed from the diode areabefore forming the Schottky barrier in step (d).
 13. A method accordingto claim 11 or claim 12, wherein the MOSFET device has a trench-gate ofwhich the gate electrode is accommodated in a trench that is etched intothe body in step (c) at windows in an etch-mask layer, and wherein anarea of the etch-mask layer is provided over the diode area to mask thediode area during the formation of the active device cells in step (c)and is removed from the diode area before forming the Schottky barrierin step (d).